1. Field of the Invention
The present invention relates to a set associative cache system and a cache memory control method, which are capable of changing the number of sets and the number of ways while keeping the number of cache blocks constant.
2. Description of the Related Art
To cope with complexity of system and improvements on the semiconductor technology, at present various studies have been made on the technology of executing a plurality of process units in parallel using a multitask OS (Operating System), a multiprocessor, a multithread processor, an on-chip multiprocessor or the like.
The “process units” in this specification indicate a system, such as an OS, a processor, such as a CPU, a program or a process to be executed, and a thread.
Through the studies, a system capable of executing plural processes in parallel can be constructed. The recent trend is to appreciate concepts of designing a system compact and sharing resources for executing a plurality of process units in parallel, leading to development of various inventions.
To make processing faster, it is inevitable to use a cache memory, which is the essential technology at present, more efficiently. As the capacity of the cache memory has an upper limit, it is important to share a cache memory between plural processes which are executed in parallel.
Under the situation, inventions on cache sharing have been made actively. Sharing a cache requires a cache system architecture that has better performances to cope with complex processing.
There is a cache system proposed which divides the cache region by the number of process units, such as systems, processors or threads, and decides, beforehand, a cache region to be used by each process unit in order to improve the performance of a cache system. Those existing cache region dividing types have the following problems.
(1) Division by Cache Set
When a cache region to be used is allocated to each process unit, different process units cannot use a cache block directly, so that a cache mishit may occur.
(2) Division by Cache Way
When the number of ways usable per process unit is fixed, the number of ways may not be sufficient for a process unit which involves many cache requests.
When the number of ways usable per process unit is made variable, if there is the number of ways may not be sufficient for a process unit which involves many cache requests, most of the ways are used by the same process unit and the other process units substantially can hardly use the cache. That is, there is a cache mishit between different process units.
(3) Division by Cache Block Unit
As a process unit which can use one cache block is fixed, when different process units use the same cache block, the contents of the cache block are all replaced before usage. That is, there is a cache mishit between different process units.
An improved cache system is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H5-20193.
The cache system can select the number of ways, which is one factor to influence the hit ratio of a cache memory, during execution of a program. The cache system can change the configuration of hit checking means according to the selected number of ways.
Another improved cache system is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H9-2582.
The cache system can select the number of ways during execution of a program The cache system can use a plurality of simultaneously readable cache regions (cache arrays). This structure can reduce cache mishits originating from contention between tasks, such as an OS and a user program, according to the changed number of ways.
The cache systems disclosed in both Japanese publications are concerned with a technique for a single processor, not a technique for a multitask OS, a multiprocessor and a multithread. Therefore, the cache systems cannot reduce cache mishits per hit process unit under a multitask OS, a multiprocessor and a multithread.
The way selecting/comparing schemes disclosed in both Japanese publications designate the maximum value of a way when a cache request is made. When the systems take a configuration which involves fewer ways than the maximum number of ways, therefore, the efficiency of using the cache may drop.